1. Field of the Invention
The present invention relates to a power amplifier enabling the improvement of delay in the rise of output power when switching a main power amplifier and a supplementary power amplifier.
2. Background Art
Currently, a GaAs-HBT (hetero-junction bipolar transistor) power amplifier is widely used as a power amplifier for mobile telephones, such as CDMA. FIG. 22 is a circuit diagram showing a conventional GaAs-HBT power amplifier. The area within the dotted-line frame is a GaAs chip, and other circuit elements are composed of chip parts and wirings formed on a module substrate.
In FIG. 22, Tr1 and Tr2 denote a former amplification element and a latter amplification element, respectively. Bias 1 denotes a former bias circuit to drive the former amplification element, and Bias 2 denotes a latter bias circuit to drive the latter amplification element.
Vc1 and Vc2 denote collector power terminals for former and latter amplification elements, respectively. Vcb denotes a power terminal for the bias circuits Bias 1 and Bias 2, and Vref denotes a terminal to apply control voltage to the bias circuits Bias 1 and Bias 2. IN denotes an RF signal input terminal, OUT denotes an RF signal output terminal, R1 to R4 denote resistors, C1 to C10 denote capacitors, and L1 and L2 denote inductors. L3 to L8 denote wirings having predetermined electrical lengths which operate as inductors. In recent years, C1, C2 and L1 for input matching and C3, C4 and L2 for inter-stage matching are also often integrated on a GaAs chip for the size reduction of a module.
FIG. 23 is a circuit diagram showing a conventional bias circuit. This bias circuit is one of the above-described former bias circuit Bias 1 or latter bias circuit Bias 2. In FIG. 23, Vref denotes a terminal to which a control voltage is applied from outside, Trb1 to Trb3, Trb7 and Trb8 denote GaAs-HBTs, Tr denotes an amplification element, and Rb1 to Rb3 and Rb5 to Rb8 denote resistors.
Am emitter follower circuit including Trb1 inputs a voltage corresponding to the control voltage to the base (input terminal) of the corresponding amplification element Tr. The RF signals inputted from the terminal RFin is inputted to the base of the amplification element Tr via a capacitor C in the input matching circuit. Then, amplified RF signals are outputted from the collector of the amplification element Tr to the terminal RFout.
This bias circuit operates so as to maintain the idle current of the former amplification element and the latter amplification element of the power amplifier against temperature change (e.g., refer to Japanese Patent Laid-Open No. 2004-343244). Here, the idle current means a bias current of a power amplifier when there is no RF input power.
FIG. 24 is a graph showing the input-output characteristics of a conventional HBT power amplifier for CDMA. When the input power Pin increases, although the idle current Ictq is constant, the output power Pout increases, and the total operating current Ict increases.
FIG. 25 is a graph showing the distortion characteristics of a conventional HBT power amplifier for CDMA. The distortion characteristics are represented by an adjacent channel leakage power (ACLR). With the increase of the output power Pout, ACLR increases. The output power Pout, the power gain Gp, and the efficiency PAE determine the characteristics of the power amplifier.
FIG. 26 is a graph showing the distribution of probabilities for the output power of a power amplifier in a CDMA terminal machine in a suburban area. The probability of low output in the vicinity of 0 dBm is highest, and the probability of maximum output in the vicinity of 27 dBm is low (e.g., refer to B. Sahu and G. A. Rincon-Mora, “A high-efficiency linear RF power amplifier with a power-tracking dynamically adaptive buck-boost supply,” IEEE Trans. MTT Vol. 52, No. 1, pp. 112-120, January 2004). Therefore, it is desired that the idle current is suppressed to be low when the output power is low, and the idle current is increased when the output power is high, to satisfy the distortion characteristics.
Therefore, a power amplifier operated by switching a main power amplifier having large idle current and a subsidiary power amplifier having small idle current has been proposed. FIG. 27 is a graph showing the output and gain characteristics of the main power amplifier and the subsidiary power amplifier. The main power amplifier has high efficiency and low distortion characteristics when output power is high as shown by (H) in FIG. 27. On the other hand, the subsidiary power amplifier has high efficiency and low distortion characteristics when output power is low as shown by (L) in FIG. 27. The main power amplifier and the subsidiary power amplifier are switched when the output power Pout is around Pout 2.
FIG. 28 is a diagram showing a chip layout of a conventional power amplifier operated by switching a main power amplifier and a subsidiary power amplifier. A GaAa chip 32 is mounted on a module substrate 31 via a die-bonding material. On the GaAa chip 32, a main power amplifier (an input matching circuit 11, a former amplification element 12, an inter-stage matching circuit 13, a latter amplification element 14, output matching circuits 15, a former bias circuit 16, and a latter bias circuit 17) and a subsidiary power amplifier (an input matching circuit 21, a former amplification element 22, an inter-stage matching circuit 23, a latter amplification element 24, output matching circuits 25, a former bias circuit 26, and a latter bias circuit 27) are formed. The former amplification element 12, the former amplification element 22, the latter amplification element 14, and the latter amplification element 24 are hetero-junction bipolar transistors (HBT).
FIG. 29 is a graph showing output power characteristics of a conventional power amplifier operated by switching a main power amplifier and a subsidiary power amplifier. The response of output power when switching the main power amplifier and the subsidiary power amplifier is slow, and a long time is consumed until the stabilization of the power level. Specifically, several hundreds of microseconds to several milliseconds were required for the stabilization of the power level, while several tens of microseconds were demanded for this. Therefore, serious problems have been caused when a conventional power amplifier is used as a power amplifier for CDMA wherein time-to-time power-level adjustment is required.
Findings obtained by the present inventors from simulations and experiments carried out for investigating the causes of the problems are as follows:
FIG. 30 is a graph showing the step response of the collector current of an HBT in base voltage driving: and FIG. 31 is a graph showing the step response of the collector current of an HBT in base current driving. The HBT itself generates heat represented by the product of the collector current Ic and the collector-emitter voltage Vce. Due to this self-heating, the transient response of the collector current Ic in base voltage driving is extremely slow (several hundreds of microseconds to several milliseconds). On the other hand, the response of the collector current Ic in base current driving is very quick (several microseconds or less). Therefore, when an emitter follower circuit that operates in a state nearly base voltage driving as shown in FIG. 23, the transient response of the collector current Ic of the HBT is slow.
Furthermore, the mutual heat interference between circuit blocks in a chip may further retard the transient response of the collector current of an HBT. This will be described below.
FIG. 32 is a graph showing the output voltage characteristics of the latter bias circuit of a subsidiary power amplifier against the heat generation of the latter bias circuit of a main power amplifier. The configuration of the latter bias circuit is as shown in FIG. 23. The interval between the latter bias circuit of the main power amplifier and the latter bias circuit of the subsidiary power amplifier is about 700 μm in Type 1, and about 200 μm in Type 2. From these data, it is known that the larger the heat Pd generated in the latter bias circuit of the main power amplifier, the lower the output voltage Vbo of the latter bias circuit of the subsidiary power amplifier.
Here, heat generated in the latter bias circuit of the main power amplifier during the operation of the main power amplifier is dissipated during the operation of the subsidiary power amplifier. However, due to the effect of the heat capacity of the module substrate and chips, a long time is consumed for heat dissipation. Therefore, the idle current of the latter bias circuit of the subsidiary power amplifier is gradually increased, and as shown in FIG. 32, the output voltage Vbo of the latter bias circuit of the subsidiary power amplifier is gradually increased. Therefore, when the main power amplifier is switched to the subsidiary power amplifier, the rise of the output power of the subsidiary power amplifier is delayed as shown in FIG. 29. Similarly, when the subsidiary power amplifier is switched to the main power amplifier, the rise of the output power of the main power amplifier is also delayed.